Since digital signal may be interfered in the process of transmission, there can be error in the transmitted data. Thus, at the receiving end, a false judgment may possibly occur.
In order to solve this problem, some parity bits can be added to the data sequence by an Error Correction Code (ECC) encoding circuit at the sending end, in order to detect and correct the erroneous data. It has been shown that numerous algorithms can support ECC, such as the common Hamming code, in which 8-bit data needs 4 parity bits and 64-bit data needs 7 parity bits. Thus, a proper algorithm may be selected according to the data length and the number of the data bits which need detection and correction.
As to different Double Data Rate (DDR) structures (DDR1/2/3), the data prefetching lengths for the typical stream in-and-out data reading are 32-bit, 64-bit and 128-bit. A reasonable and compromising solution is to use 7 parity bits or 8 parity bits for a 64-bit data (according to different ECC algorithms), as shown in FIGS. 1 and 2.
Nevertheless, as the presence of the Data Mask (DM), it is not easy for the DRAM to realize detection and correction functions. That is, when external data are written to DRAM, since one or more Bytes may be masked off, the data previously stored in the storage unit will not be overwritten. In this way, the ECC encoding process will not generate parity bits successfully, as shown in FIG. 3.
In order to solve this problem, the simplest method is to split 64-bit data into 8 groups and each group consists of 8-bit data (one Byte), precisely corresponding to the mask length of DM, so as not to be effected by DM. Nevertheless, since each 8-bit data needs 4 parity bits, making the area of the whole storage array increase by 50%, the cost of DRAM is significantly increased. Therefore, it desperately needs a solution to address the problems and defects brought out by DM.